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SL1466
Wideband PLL FM Demodulator Preliminary Information
DS 3979 2.2 August 1997
SL1466
The SL1466 is a wideband PLL FM demodulator, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of external local oscillator tank and loop filter components, to form a complete PLL system operating at 403 or 480MHz. An AFC system is provided, whose output signals can be used to correct for any frequency drift at the head end local oscillator.
GND DIGF LO DIGF HI AFC SET AFC WINDOW OSC V CC OSC + OSC - OSC GND VCO GAIN SET VIDEO DRIVE VIDEO POL SELECT NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V CC VIDEO FB+ VIDEO + VIDEO - VIDEO FB- IF V CC IF IPB IF IP IF GND RF AGC SET AGC TIME CONSTANT IF AGC SET NC RF AGC CONTROL
FEATURES I Single chip PLL system for wideband FM demodulation I Simple low component count application I Fully balanced low radiation design I High operating input sensitivity I 2 stage AGC detect for control over internal and external AGC stages I Low distortion video output drive I Video polarity invert I Digital AFC with window adjust I ESD protection (Normal ESD handling procedures should be observed)
QP28
Fig.1 Pin connections - top view
APPLICATIONS I Satellite receiver systems I Data communications systems ORDERING INFORMATION
SL1466/KG/QP1S
PHASE DETECTOR 27 26 25 24 VIDEO FB+ VIDEO + VIDEO - VIDEO FB-
IF IP IF IPB
21 22
AGC AMP
AGC DETECT ON CHIP VCO
11 12
VIDEO DRIVE VIDEO POLARITY SELECT
S/H AFC NC 16 REF
4
AFC SET
NC RF AGC CONTROL 28 1
13 15
5 2 3 14 NC 19 RF AGC SET 18 17 78 LO TANK 10 VCO GAIN SET AGC TIME IF CONST AGC SET
AFC WINDOW DIGF LO DIGF HI
Vcc GND
Fig. 2 Block diagram
SL1466
ELECTRICAL CHARACTERISTICS
TAMB = -20C to +80C, VCC = +4.75 to +5.25V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Pin Min Supply current, Icc RF Section Operating frequency Input sensitivity Input overload Input Impedance Internal AGC AMP range VCO Section VCO dF/dV (Ko) VCO supply sensitivity VCO temperature sensitivity Video section Phase detector gain (Kd) Loop amplifier input impedance Video drive output swing Video drive output Impedance Video drive luminance non - linearity Differential gain Differential phase Tilt Base line distortion Intermodulation Signal/noise Video polarity select input Low Video polarity select input High Video polarity switch leakage current Video polarity switch leakage current Positive to negative video gain balance AFC section AFC window minimum widths AFC output high voltage AFC output low voltage 2,3 2,3 VCC-0.4 0 0.44 VCC 0.4 MHz V V Deadband measured at 90% of AFC high voltage 11 11 11 11 11 11 11 12 12 12 12 11 VCC 10 10 1 2 2 2 1.0 -46 58 VEE 0.5 -40 % % Deg % dB dB dB V V A A dB 75 load 75 load 75 load 75 load 75 load 75 load, see note 1 75 load, see note 2 Negative polarity Positive polarity VCC=5.25V VCC=5.25V Vin=0V Vin=5.25V 11 11 11 0.5 570 0.9 1.8 100 V/rad Vp-p Vp-p Differential loop filter R1 in note on loop parameters Into 75, 18MHz frequency deviation Into 1K, 18MHz frequency deviation At 27C 6,23,28 21, 22 21, 22 21, 22 21, 22 50 10 6,7,8,9 7,8 54 1.0 0.05 0 Value Typ 65 480 -60 -7 75 Max mA MHz dBm dBm dB MHz/V MHz/V MHz/C At 27C 0-55C, VCC=5V, 750ppmNTC, 0.5pF tuning cap. At 27C Units Conditions
2
SL1466
NOTE: 1. Product of input modulation f1 at 4.43MHz p-p deviation and f2 at 6MHz, 2MHz p-p deviation, (PAL chroma and sound subcarriers). 2. Ratio of luminance bar amplitude (100% white), 13.5MHz p-p deviation, to output rms noise in 6MHz bandwidth with no input modulation. 3. The above characteristics were measured in the Application circuit shown in Fig.10, with an input power of -50dBm and(RFIN) =480MHz, unless otherwise stated.
ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Characteristic Min Max Units Conditions
Supply voltage RF input voltage Storage temperature Junction temperature QP 28 package thermal resistant, chip to ambient QP 28 package thermal resistance, chip to case ESD protection
-0.3 -55
7 2.5 125 150 93 34
V Vp-p C C C/W C/W kV Mil std 883B method 30115 cat 1.
2
PIN DESCRIPTION PIN NO 1 2 3 4 5 PIN NAME GND DIGFLO DIGFHI AFCSET AFCWINDOW DESCRIPTION Chip ground Flag = high when F (local oscillator) < F (IFIN) - F (WINDOW)/2 Flag = high when F (local oscillator) >F (IFIN) + F (WINDOW)/2 Connected to VCC Control input current sink sets width of AFCWINDOW F =2250 Ko x I where I is the AFCWINDOW current F is the window width and Ko is the VCO gain 6 7 8 9 10 11 12 13 14 15 16 17 18 OSC VCC OSC+ OSCOSC GND VCO GAIN SET VIDEO DRIVE VIDEO POL SELECT NC NC RF AGC CONTROL NC IF AGC SET AGC TIME CONSTANT Connect to VCC via 6k8 Ohm resistor Control input current source. Pulse at carrier frequency F(IFIN) with mark/space proportional to applied device AGC gain. Use external R-C to set time constant. 47K, 100nF Control output current to tuner AGC control port. See Fig. 4. Oscillator VCC External tank External tank Oscillator ground Control voltage input to set VCO GAIN. Connect to VCC Video output (1K, 1.8V p-p) Control voltage input to set Video polarity. 0 Volts = inverted, 5 Volt = normal (Note units are MHz, Amps and Volts)
3
SL1466
PIN DESCRIPTION PIN NO 19 20 21 22 23 24 25 26 27 28 PIN NAME RF AGC SET IF GND IF IP IF IPB IF VCC VIDEO FBVIDEOVIDEO+ VIDEO FB+ VCC DESCRIPTION IF stage ground IF input (preferred input for single ended use) IF input IF stage VCC Loop amp negative input. Connected to VIDEO + via loop network Loop amp negative output Loop amp positive output Loop amp positive input. Connected to VIDEO- via loop network Chip VCC (Note units are MHz, Amps and Volts)
Connect to VCC via 1.8K resistor
FUNCTIONAL DESCRIPTION
The SL1466 is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and requiring a minimal external component count. It contains all the elements required for the construction of a phase locked loop circuit, with the exception of tuning components for the local oscillator. Also included is an AFC detector circuit for generation of error signals to correct for any frequency drift in the outdoor unit local oscillator. A block diagram is shown in Fig. 2 and a typical application in Fig. 6. The internal pin connections are shown in Fig. 1. In normal applications the second satellite IF of typically 403.2 or 479.5 MHz is fed to the RF preamplifier, which contains a two stage level detect circuit. This generates two AGC signals, one of which controls the gain of the internal IF amplifier stage and one which can be used for controlling the gain of an external RF preamplifier so maintaining a fixed level to the input of the phase detector for optimum threshold, performance. The typical AGC curves are shown in Fig. 4. The output of the preamplifier is fed to the mixer section which is of a balanced design for low radiation. In this stage the IF signal is mixed with the local oscillator signal, which is generated by an on board oscillator. The oscillator is tuned internally, requiring only an external fixed LC tank and is optimised for high linearity over the normal deviation range. Typical frequency versus video drive voltage response for the oscillator is shown in Fig. 8. This response was measured with a modulated carrier. The compensated oscillator temperature stability is typically 0.05MHz/C. The gain of the oscillator is nominally Ko = 54MHz/Volt. Note: Because there is a x3 amplifier in the video output section, the overall chip gain (MHz/V) is one third of the VCO gain or18MHz/Volt. The gain may be set accurately by means of potential divider connected to Pin 10. (+4.5V) The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop amplifier transfer characteristics. The output of the loop amplifier is referenced so as to eliminate V CC dependence of the VCO. The loop amplifier drives a buffer amplifier, which can be connected to a 75 Ohm load or a high impedance stage to give greater linearity and approximately 6dB higher demodulated signal. The video polarity can be inverted depending on the sense of the video polarity select input; open circuit or a resistor to V CC gives positive video whereas a resistor to V EE gives negative video.
R2 PHASE DETECTOR GAIN = Kd VOLT/RAD RF INPUT R1
C1 X3 VIDEO DRIVE
VCO VCO GAIN = Ko RAD/SEC/VOLT
VIDEO
Fig. 3 Design of PLL loop parameters
4
SL1466
The SL1466 is normally used as a type 2 second order loop and can be represented by the above diagram. for such a system the following loop parameters apply. T 1= C1 R1 T 2= C1 R2 and T 1= Ko KD/ n2 T2=2 /n where: KO is the VCO gain in radians seconds per volt KD is the phase detector gain in volts per radian n is the natural loop bandwidth is the loop damping factor From these factors the loop 3dB bandwidth can be determined from the following expression; 2 = 2(22 + 1) + 2 ((22 + 1) + 1 n n 3dB which approximates to 3dB = 2n, when >>1 N.B. VCO gain within the PLL is three times higher than at the video drive pin due to gain in the output stage. NOTE: R1 is the loop amplifier input resistor. R2 and C2 are the generic designators for the loop components R7-R9 and C9, C14 on the circuit diagram.
AGC FACILITY
A sophisticated two stage level detect circuit has been provided which will control both internal IF AGC and external tuner AGC amplifiers in order to maintain a fixed level to the input of the phase detector of around -20dBm for optimum threshold performance. The internal AGC amplifier provides 50dB of gain adjust and the external AGC control provides for 15dB of gain adjust, thus covering 65dB of dynamic range at the tuner input. The RF output current RF AGC CONTROL can be converted to a positive gradient control voltage by an external resistor. AFC FACILITY The SL1466 contains a digital frequency error detect circuit, which generates an output consisting of two logic flags, DIGFHI and DIGFLO, dependant on whether the LO frequency is above or below the input frequency. These flags have an overlap region where both are high; this is equivalent to the deadband window. The function of the AFC outputs is shown in Fig. 7 and the accompanying Table.
RFC AGC CONTROL CURRENT (A) 400 350 300 250 200 150 100 50 0 -90 -70 -50 Pin dBm -30 -10 1V 2V 3V TC RFCONT 4V
AGC TIME CONSTANT (V)
Fig. 4 RF AGC control current and AGC time cinstant voltage vs Input power
5
SL1466
Vcc
Vcc 62 A DIGFHI DIGFLO VREF
4.8k VEE VEE
AFC AFC KEY SET
AFC DIGFLO, DIGFHI outputs (Pins 2, 3)
AFCAFC SET (Pin 4) 4) KEY INPUT (Pin
Vcc
AFC WINDOW 50 50
OSC OSC VREF;Vcc -2.5V OSC
2.5mA VEE
3mA VEE
2.5mA VEE
AFC WINDOW (Pin 5)
OSC (Pin 7, 8)
VCC
VCC 125 A 125 A
VCC
60
VIDEO DRIVE
4.8k
125 A
VCC/2
3.3mA
VCO GAIN VCO GAIN ADJUST SET
VEE VEE
VCO GAIN ADJUST (Pin 10) VCO GAIN SET (Pin 10)
VIDEO DRIVE (Pin 11)
Fig. 5a SL1466 I.O.ports internal circuitry
6
SL1466
Vcc 160k RF AGC CONTROL
2.5V VEE 5k VIDEO POLARITY VEE VEE
VEE
VIDEO POLARITY (Pin 12)
IF AGC SET
RF AGC control (Pin 15) RF AGC CONTROL (Pin 15)
Vcc
VREF Vcc -3.15V ,
VREF;Vcc -2.4V
AGC TIME CONSTANT
IF AGC SET (Pin 17) IF AGC SET (Pin 17)
AGC TIME CONSTANT 18) AGC TIMECONSTANT (Pin(Pin 18)
VCC
RF AGC SET
415
415
VREF;Vcc -2V
350 IF IP
350 IF IP
2m VEE
RF AGC SET (Pin 19)
IF IP (Pins 21, 22)
Fig. 5b SL1466 I.O ports internal circuitry
7
SL1466
VCC
VCC VCC
415
415
VIDEO-
VIDEO+
350 IF IP
350 IF IP
500 A 500 A
2m VEE
VEE
VEE
IF IP (Pins 21, 22)
VIDEO+, VIDEO- (Pins 25, 26)
Fig. 5c SL1466 I.O ports internal circuitry
H9 1 2 H8 3 4 R1 100K
C12a 100nF
C12b 100pF H1 1 2 C12b C12a 100pF 100nF
1
2
3
GND DIGFLO DIGFLHI
VCC
AFCSET 5 AFCWINDOW VCC Tayo Yudan UMK107 UK0R5CZ-B 6 OSCVCC 0.5p. 750PPM NTC 7 OSC+ C3b C3a C1 8 L1 100nF 100pF OSC4.5T,3MM,0 56" 9 OSCGND C2a 100nF 10 VCOGAINSET VCC 11 VIDEODRIVE SKT2 C2b 100F VIDEO OUT 12 BNC VIDEOPOL 13 NC VCC H7 14 NC 1 2 1 2 C10a 10uF VCC C10b 1 100nF 2 S1 SW DIP-2 IC1 SL1466_IEE
VCC VIDEOFB+ 27 26 VIDEO+ VIDEO- 25 VIDEOFB- 24 23 IF VCC 22 IF IP C7a 21 IF IP 100nF 20 IF GND 19 RFAGCSET 18 AGCTIMECONST 17 IF AGCSET 16 NC RFAGCCONT 15
28
VCC R9 1K3 R7
C13 1pF
C14 330pF
C9 330pF 1K3 C8 1pF C6 10nF C7b 100pF R10 50 C5 10nF SKT1 SMA RF IN
2 R4 4K7 C4 100nF
VCC C11 100nF
R11 10K 21 H5
R3 6K8 2
R5 1K8
1
4 3
21 H4
1 H3
Fig. 6 Typical application circuit. Note: Loop component values may need re-optimising on Application and VCO gain setting.
8
SL1466
WINDOW
DIGFLO
DIGFHI
IFIN
f(LO)
Fig. 7 SL1466 digital AFC output
FREQUENCY ERROR f(LO) Below window f(LO) Within window f(LO) Above window DIGFLO 1 1 0 DIGFHI 0 1 1
4.5
4
VIDEO DRIVE Volts
3.5
Down Up
3
2.5
2.
1.5 420 430 440 450 460 470 480 490 500 510 520 530 540
RF IN MHz
Fig.8 VCO performance (S curve characteristics)
9
SL1466
APPLICATION NOTES Tuning procedure
The component values shown in the applications circuit Fig. 6 are optimised for operation at an IF of 479.5MHz. The AFC circuit can be used to fine tune the external tank as follows: With the SL1466 connected as in the test set up Fig. 11 or its equivalent using 75 cables. Set the video generator for 1V p-p output. Set the satellite test transmitter for a carrier frequency of 479.5MHz, frequency deviation 13.5MHz, power level -30dBm. Turn on the pre-emphasis filter. Monitor the voltage levels on Pin 2 (DIGFLO) and Pin 3 (DIGFHI). Adjust the tank coil by squeezing it slightly until the signal on both Pins goes high (i.e. > Vcc -0.4 Volts). These Pins remain high provided the LO frequency is tuned to within the AFC WINDOW aperture,( 0.22MHz). I Calculate R7 (R9) and C9 (C14) based on n = 2.46MHz, =2.6 and connect as in Fig. 5. I Set the video generator for 1Vp-p composite video and the test generator for a carrier frequency of 479.5MHz, frequency deviation of 13.5MHz and power level -30dBm. I Turn on the pre-emphasis filter. Use the 15kHz test pattern to give black/white screen. I Monitor the video analyser or TV set. I Adjust the de-emphasis filter until the bar amplitude is 1Vp-p or 0% error. Reduce transmitter power level until sparklies or streaking appear. I Adjust component values for minimum power level when streaking and sparklies occur together.
Optimising the loop components
The network connected from Pin 26 (VIDEO+) to Pin 24 (VIDEOFB-) and from Pin 25 (VIDEO-) to Pin 27 (VIDEO FB+) forms the loop filter. The components shown are based on a natural frequency n of 2.46MHz ( n =2x x2.46 Mrads/s ) and damping factor =2.6, and assuming Ko = 54MHz/V. The closed loop gain of the receiver (i.e. the ratio of the output amplitude to the input carrier frequency variation versus frequency) has a low pass filter characteristic. Its roll off is determined by the natural frequency whilst its in band flatness is determined by the damping factor. Both factors will affect the 3dB bandwidth as discussed earlier. A narrow bandwidth will cause loss of high frequency resolution whilst a large bandwidth will degrade the overall signal/noise in the output waveform. Thus a selection procedure might be as follows:
AGC settings
The signal level at the input to the limiter preceding the phase detector is maintained at an level of around -20dBm or more by an internal (device) AGC and an external (tuner) AGC circuit. Current pulses at the carrier frequency with mark/space proportional to this input power are sourced out of pin 18 (AGC TIME CONSTANT). These are smoothed and turned into a voltage by the external components R4, C4. The time constant R4 C4 should be adjusted so that the expected signal fading rate can be tracked but its value is not critical, 5mSec typically. Fig. 4 shows a typical external AGC control curve. Also shown is the AGCTIMECONST voltage which is an indication of the level of internal AGC gain being applied, (the control range is the flat part of the curve).
10
SL1466
COMPONENT SIDE
Fig. 9 Test demo PCB
11
SL1466
H9 1 2 H8 3 4 R1 100K
C12a 100nF
C12b 100pF H1 1 2 C12b 100pF
1
2
3
GND DIGFLO DIGFLHI
VCC
28
VCC R9 1K3
C13 1pF
C12a 100nF
AFCSET 5 AFCWINDOW VCC VCC Tayo Yudan UMK107 UK0R5CZ-B 6 OSCVCC 0.5p. 750PPM NTC 7 C3b OSC+ C3a C1 8 L1 100nF 100pF OSC4.5T,3MM,0 56" 9 OSCGND C2a 100nF 10 VCOGAINSET VCC 11 VIDEODRIVE SKT2 C2b 100F VIDEO OUT 12 BNC VIDEOPOL 13 NC VCC H7 14 NC 1 2 1 2 C10a 10uF VCC C10b 1 100nF 2 S1 SW DIP-2 IC1 SL1466_IEE
VIDEOFB+ 27 26 VIDEO+ 25 VIDEOVIDEOFB- 24 IF VCC IF IP 23 22 C7a 21 IF IP 100nF 20 IF GND 19 RFAGCSET 18 AGCTIMECONST 17 IF AGCSET 16 NC RFAGCCONT 15
C14 330pF
R7 C9 330pF 1K3 C8 1pF C6 10nF C7b 100pF R10 50 C5 10nF SKT1 SMA RF IN
H2
2
R4 4K7
C4 100nF
VCC C11 100nF
R11 10K 21 H5
R3 6K8 2
R5 1K8
1
4 3
21 H4
1 H3
Fig. 10 Test/Demo circuit diagram
Video Monitor
R&S SPGF Waveform Generator
Pre-Emphasis
Modulator/ Upconverter
SL1466
De-Emphasis
R&S UAF Video Analyser
479.5MHz f = 13.5MHz R&S SFZ Satellite Test Transmitter
Fig. 11 Test set up
12
SL1466
13
SL1466
14
SL1466
15
SL1466
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package information, please contact your local Customer Service Centre.
9*80/9*98 (0*386/0*393) PIN 1
0-8 0*33 (0*013) x 45 REF.
3*81/3*99 (0*150/0*157)
PIN 1 REF. SPOT
5*80/6*20 (0*230/0*244) 0*41/0*89 (0*016/0*035)
28 LEADS AT 0*63 (0*025) NOM. SPACING
0*64/0*76 (0*025/0*030)
0*17/0*25 (0*007/0*010)
1*40/1*55 (0*055/0*061)
1*55/1*73 (0*061/0*068)
NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your Mitel Semiconductor Customer Service Centre for further information.
0*17/0*30 (0*007/0*012)
0*127/0*25 (0*004/0*010)
28-LEAD SUBMINIATURE PLASTIC DIL - QP28
HEADQUARTERS OPERATIONS MITEL SEMICONDUCTOR Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 MITEL SEMICONDUCTOR 1500 Green Hills Road, Scotts Valley, California 95066-4922 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576/6231
Internet: http://www.gpsemi.com CUSTOMER SERVICE CENTRES G FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07 G GERMANY Munich Tel: (089) 419508-20 Fax : (089) 419508-55 G ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 G JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 G KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 G NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 G SOUTH EAST ASIA Singapore Tel:(65) 3827708 Fax: (65) 3828872 G SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 G TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 G UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) Mitel Corporation 1998 Publication No. DS3979 Issue No. 2.2 August 1997 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
16
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

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